Abstract: The wireless networks for industrial automation process automation (WIA-PA) system on chip (SoC) is the core component of WIA-PA wireless devices and occupies a large proportion of the total power consumption of the device. According to the application environment and working characteristics of WIA-PA devices, we study a variety of low-power optimization methods and propose a comprehensive low-power optimization strategy for WIA-PA SoC. The strategy combines multiple methods, e.g., gate control clock, asynchronous circuit application, system-level optimization, and process optimization. In addition, the strategy achieves both static and dynamic power consumption optimization by considering different circuit types and design levels. WIA-PA SoC has been completed for two times of type-out. The first time completes functional verification, whereas the second time realizes the proposed low-power optimization. We test the sample chips two times. Experimental data of power consumption reveal that the dynamic power consumption of the optimized sample chip is reduced by 71.2% and the static power consumption is reduced by 99.5%. The comparison results demonstrate the effectiveness of the proposed optimization strategy.