Abstract: A FPGA(field programmable gate array) design and implementation scheme is proposed according to the characteristic of IB-IWT(interpolating bi-orthogonal integer wavelet transform) of real-time image compression.Firstly, through analysis of IB-IWT,a real-time image compression scheme for hardware implementation is put forward.Then, high performance FPGA is selected as hardware processing platform and the key technology of hardware implementation based on the algorithm is studied,such as wavelet transform,wavelet coefficients coding,boundary processing and finite word effects.Fast realization structure of(5,3) wavelet transform and wavelet coefficients coding in FPGA are proposed. Finally,the image is compressed by FPGA.By taking advantages of ideas of flag maps and parallel SPIHT(set partitioning in hierarchical trees) algorithm,the resourceful property in FPGA is greatly utilized by the scheme.The experimental results show that the scheme is greatly suitable for real-time hardware implementation due to its low computational complexity, small memory requirement and high real-time processing speed.