RS+交织+卷积码级联纠错的FPGA实现

FPGA Implementation of Cascade Correction for RS,Interleaved and Convolutional Codes

摘要: 为了提高编解码速率，更好地满足实时收发系统的要求，本文提出了采用由纯硬件电路构成的现场可编程逻辑门阵列（Field Programmable Gate-Array，FPGA）取代CPU系统的纠错码策略．该策略先把RS（Reed Solomon）、交织、卷积编解码分别模块化，然后通过端口映射方式对它们进行逻辑组织以实现整个编解码的级联．分析表明，用FPGA构成的纠错码系统不仅使电路大大简化，稳定性得到极大提高，而且可编程逻辑器件的高智能化使整个系统的设计、调试周期大大缩短．

Abstract: In order to increase coding and decoding rates and to meet the demand of real-time transceiver system,this paper presents an error-correcting code strategy which uses field programmable gate-array(FPGA) composed of pure hardware circuit to replace the CPU system.The strategy modularizes the encoding and decoding of Reed Solomon(RS),interleaved and convolutional codes respectively,and then gets them together logically by means of port mapping to concatenate the whole process of coding and decoding.Analysis shows that the error-correcting decoder with FPGA greatly simplifies the circuit and makes it more stable,and the high intelligence of programmable logic devices greatly shortens the design and debugging period of the whole system.